1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and, more particularly, to a contact portion for connection between interconnection layers.
2. Description of the Related Art
In general, as the integration density of a semiconductor integrated circuit device becomes greater, the resistance of its signal transmission lines increases to thereby increase delay of a signal to be transmitted. In a semiconductor memory, for example, the gate electrodes of MOSFETs for selection (cell switching) of memory cells are extended to be used as signal lines (word lines). A polysilicon layer is generally used to form the gate electrodes. Polysilicon has a resistivity larger than metal, and therefore the wiring resistance of the signal lines increases as the integration density becomes large, thereby increasing the delay of address signals. Increase in the delay time of address signals lowers the access speed.
In order to suppress the delay of address signals to a minimum, conductive layers such as metal layers, having a lower resistivity than the signal lines (word lines) which are formed to extend from the gate electrodes of cell switching MOSFETs, are formed extending along the signal lines on an insulation film which is formed on the signal lines in the prior art. The signal line is electrically connected to the conductive layer via a contact hole or holes formed in the insulation film. Such contact portions are formed for each signal lines. Thus, the signal line having a large wiring resistance is connected in parallel with the conductive layer having a resistivity smaller than the signal line, reducing the resistance of the word lines and suppressing the delay time of address signals.
However, with the construction described above, it is necessary to make a portion of the signal line wider so as to provide a sufficiently large margin for mask alignment so that good contact between the signal line and conductive layer can always be attained. The contact may be made imperfect when, for example, masks for patterns of the contact hole and signal line are displaced from each other. For this reason, when a large number of signal lines are juxtaposed, the signal lines cannot be closely arranged because of the presence of the wide portions of the signal lines. Further, it is desired to form a large contact hole in order to reduce the contact resistance between the signal line and conductive layer. However, if the contact hole is formed larger, it is necessary to enlarge the wide portion of the signal line by the margin for mask alignment, making it necessary to increase the distance between the signal lines. This further limits the high integration density. In contrast, if the signal lines are closely formed in order to enhance the integration density, the contact resistance will increase.
As described above, the contact portion of the prior art semiconductor integrated circuit device is disadvantageous in that it is difficult to attain the high integration density when the wide portion of the signal line is provided, or the contact resistance will increase when the signal lines are closely formed to enhance the integration density.